Interconnection and packaging of solid-state circuits

The growing interaction between the technologies used to interconnect and package solid-state circuits, the circuit design process, and the performance of such circuits in a system or subsystem is reviewed. The nature of this interaction is discussed at all levels of interconnection and packaging for silicon integrated circuits, and examples of novel developments which present further opportunities to the circuit designer are given. Particular attention is given to the emerging multichip module packaging concept, which offers a similar level of circuit complexity and integration to wafer-scale integration