DocumentCode
1172064
Title
An enhanced technique for simulating short-circuit power dissipation
Author
Yacoub, Ghassan Y. ; Ku, Walter H.
Author_Institution
California Univ., San Diego, CA, USA
Volume
24
Issue
3
fYear
1989
fDate
6/1/1989 12:00:00 AM
Firstpage
844
Lastpage
847
Abstract
A circuit-simulation technique which permits the measurement of the average short-circuit power dissipation component in integrated circuits using SPICE is presented. It is an extension of a previously presented scheme by S.M. King (see ibid., vol.21, no.5, p.889-91, 1986) which measures average power dissipation while circuits are being simulated. The extended technique is most appropriate for low-power circuit design. It can be applied effectively to any complementary circuit structure, such as CMOS, that does not permit current flow (other than leakage current) during steady-state operation. Results for differently W p/W n ratioed W p/W n CMOS circuits are shown
Keywords
CMOS integrated circuits; circuit CAD; digital simulation; CMOS; SPICE; circuit-simulation technique; leakage current; low-power circuit design; short-circuit power dissipation; steady-state operation; Circuit simulation; Circuit synthesis; Current measurement; Leakage current; Power dissipation; Power measurement; Radio control; SPICE; Steady-state; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.32050
Filename
32050
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