MPEG2 video codec using image compression DSP

Author

Akiyama, T. ; Aono, H. ; Aoki, K. ; Ler, K.W. ; Wilson, Brian ; Araki, T. ; Morishige, T. ; Takeno, H. ; Sato, A. ; Nakatani, S. ; Senoh, T.

Author_Institution

Corporate Product Dev. Div., Matsushita Electr. Ind. Co. Ltd., Japan

Volume

40

Issue

3

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

466

Lastpage

472

Abstract

An MPEG2 digital video codec was developed. We estimated the amount of calculation power requested for MPEG2 and designed the architecture of the codec. In order to make the codec compact, we developed an integrated image compression digital signal processor (called VDSP2). The VDSP2 integrates four different types of processors in the architecture that allows them to operate in parallel. The device is capable of both encoding and decoding the MPEG2-based algorithm by changing programs on the same chip. We also developed new dedicated hardware for motion estimation, which consists of two-pixel precision estimation and full and half pixel precision estimation. The codec is capable of processing MPEG2 main profile at main level in real-time at broadcast resolutions

Keywords

codecs; data compression; digital signal processing chips; image coding; motion estimation; parallel architectures; video equipment; video signals; MPEG2 digital video codec; VDSP2; broadcast resolutions; codec architecture; decoding; encoding; image compression DSP; motion estimation; parallel processors; real-time processing; Broadcasting; Decoding; Digital signal processing; Digital signal processors; Hardware; Image coding; Motion estimation; Signal processing algorithms; Transform coding; Video codecs;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.320829

Filename

320829