High speed video compression testbed

Author

Cheng, Ching-Min ; Wu, Chien-Hsing ; Pei, Soo-Chang ; Li, Hungwen ; Jeng, Bor-Shenn

Author_Institution

Telecommun. Lab., Minist. of Commun., Chung-Li, Taiwan

Volume

40

Issue

3

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

538

Lastpage

548

Abstract

This paper proposes a parallel processing architecture for a video compression testbed. Experiments for video coding algorithms can be performed and evaluated under this parallel processing architecture. The features of this testbed include (1) simulations of various hardware architectures, (2) test of specialized video compression circuits, and (3) testing ASICs for embedded applications as direct replacement of algorithms that have been certified. We illustrate its implementation, performance evaluation and benchmarking via JPEG/MPEG applications

Keywords

application specific integrated circuits; image coding; integrated circuit testing; parallel algorithms; parallel architectures; video signals; ASIC testing; JPEG/MPEG applications; benchmarking; embedded applications; hardware architectures simulation; high speed video compression testbed; parallel processing architecture; performance evaluation; video coding algorithms; video compression circuits; Circuit testing; Digital signal processors; Hardware; Parallel processing; Signal processing algorithms; System testing; Telecommunication computing; Transform coding; Video compression; Videoconference;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.320839

Filename

320839