DocumentCode
1173983
Title
Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching
Author
Masahara, Meishoku ; Liu, Yongxun ; Hosokawa, Shinichi ; Matsukawa, Takashi ; Ishii, Kenichi ; Tanoue, Hisao ; Sakamoto, Kunihiro ; Sekigawa, Toshihiro ; Yamauchi, Hiromi ; Kanemaru, Seigo ; Suzuki, Eiichi
Author_Institution
Nanoelectronics Res. Inst., Ibaraki, Japan
Volume
51
Issue
12
fYear
2004
Firstpage
2078
Lastpage
2085
Abstract
A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.
Keywords
MOSFET; elemental semiconductors; etching; ion implantation; nanoelectronics; silicon; 100 nm; 12 nm; Si; alkaline solution; drain regions; implanted impurities; ion bombardment damage; ion species; ion-bombardment-retarded etching; short-channel effect immunity; source regions; ultrathin channel vertical DG MOSFET; vertical type double-gate MOSFET; vertical ultrathin channel formation process; wet etching; Costs; Dry etching; Impurities; Ion implantation; Lithography; MOSFET circuits; Scalability; Silicon on insulator technology; Usability; Wet etching; 65; DG; Dopant ion implantation; MOSFET; hot alkaline solution; ion-bombardment-retarded etching; ultrathin channel; vertical double gate; wet etching;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2004.838335
Filename
1362971
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