• DocumentCode
    1175057
  • Title

    Behavioral to structural translation in a bit-serial silicon compiler

  • Author

    Hartley, Richard I. ; Jasica, Jeffrey R.

  • Author_Institution
    Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
  • Volume
    7
  • Issue
    8
  • fYear
    1988
  • fDate
    8/1/1988 12:00:00 AM
  • Firstpage
    877
  • Lastpage
    886
  • Abstract
    After a brief discussion of previous work in the field of behavioral-to-structural translation, the bit-serial architecture which is the target of the bit-serial compiler is discussed. The bit-serial language (BSL) is then defined, and the details of the behavioral-to-structural translation are given
  • Keywords
    circuit layout CAD; behavioral-to-structural translation; bit-serial architecture; bit-serial language; bit-serial silicon compiler; Arithmetic; Circuits; Computer architecture; Delay; Flow graphs; Linear programming; Scheduling algorithm; Signal processing algorithms; Silicon compiler; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.3219
  • Filename
    3219
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1175057