A Novel Low-Cost Trigate Process Suitable for Embedded CMOS 1T-1C Pseudo-SRAM Application

A novel trigate process is described in this paper for low-cost embedded CMOS-based one transistor-one capacitor (1T-1C) pseudo-static-random-access-memory (pseudo-SRAM) applications. By utilizing hydrogen anneal and a selective hard mask on the capacitor, the pass transistor fin height can be reduced while keeping the capacitor height intact. This will allow us to maximize cell capacitance while minimizing the leakage and other parasitic components related to the pass transistor that can lead to the realization of an optimum 1T-1C pseudo-SRAM cell. Device characteristics and physical cross sections are presented to demonstrate the feasibility of this process. The high-k-based cell offers a very compelling size advantage using this technique over its six-transistor SRAM counterpart which is shown using TCAD-based simulations.