A 32-bit carry lookahead adder using dual-path all-N logic

Author

Yang, Ge ; Jung, Seong-Ook ; Baek, Kwang-Hyun ; Kim, Soo Hwan ; Kim, Suki ; Kang, Sung-Mo

Author_Institution

Nvidia Corp., Santa Clara, CA, USA

Volume

13

Issue

8

fYear

2005

Firstpage

992

Lastpage

996

Abstract

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Keywords

CMOS integrated circuits; adders; circuit simulation; logic design; 0.35 micron; 32 bit; ANT; CMOS chip; CMOS technology; DPANL adder; all-N transistor; dual-path all-N logic; dynamic logic circuit; lookahead adder; low power design; post-layout simulation; Adders; CMOS logic circuits; CMOS technology; Cryptography; Embedded system; Field programmable gate arrays; Frequency; Hardware; Information security; Logic design; CMOS; dynamic-logic circuit; high performance; low-power design;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2005.853605

Filename

1512189