Multiple single input change test vector for BIST schemes

In VLSI Industry testing is an essential process for making the assurance functionality of the chip. This paper is focusing one of the test methodology called built-in-self-test (BIST). To introduce a novel test pattern generator (TPG) called multiple single input change (MSIC) TPG for test the modules of the chip. This TPG generates single input change (SIC) test vectors in multiple scan chains. Scan chains count is equal to the number of modules inside the chip. MSIC test vectors are generated here with a re-configurable Johnson counter and a fixed seed values. Seed is a pre-defined bit for MSIC pattern generator based on the modules available in the chip. Bit EX-OR operation is performed between the Re-configurable Johnson counter and the seed. Analysis result shows that the produced MSIC sequences have the features of uniform distribution and low transition density. Simulation results with S344 benchmark demonstrate that MSIC can save the test power by 7.5%.