• DocumentCode
    1181322
  • Title

    High-Density Through Silicon Vias for 3-D LSIs

  • Author

    Koyanagi, Mitsumasa ; Fukushima, Takafumi ; Tanaka, Tetsu

  • Author_Institution
    Dept. of Bioeng. & Robot., Tohoku Univ., Sendai
  • Volume
    97
  • Issue
    1
  • fYear
    2009
  • Firstpage
    49
  • Lastpage
    59
  • Abstract
    High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.
  • Keywords
    atomic layer deposition; chemical vapour deposition; elemental semiconductors; large scale integration; silicon; 3D LSI; Si; atomic layer deposition method; high-density through silicon vias; low-pressure chemical vapor deposition; poly-Si deposition; three-dimensional large-scale integration; Atomic layer deposition; Chemical technology; Chemical vapor deposition; Image sensors; Large scale integration; Microprocessors; Silicon; Testing; Through-silicon vias; Tungsten; 3-D system-in-package (SiP); Microbump; three-dimensional (3-D) large-scale integration (LSI); through silicon via (TSV); wafer bonding; wafer thinning;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/JPROC.2008.2007463
  • Filename
    4796288