Systematic fault simulation in an analog circuit simulator

With the recent increase in both fault isolation and fault tolerant design, automated and systematic methods of analyzing fault situations and their impact on the operation of solid-state circuitry are becoming increasingly important. In this paper we will explore the philosophy and techniques behind the design of a system for simulating various catastrophic failures in integrated circuits which is being implemented in a commercially available nodal circuit simulator ISPICE. We address the issues of how certain failure conditions can be identified and simulated, how certain sets of such conditions can be identified and used to reduce the cost of such a simulation without impacting the results, and how well structured reports can reduce large volumes of data to easily interpreted results. Finally, we also explore some of the more elaborate analysis and reporting techniques we expect to include in future implementations of automated fault diagnosis software.