DocumentCode
1184788
Title
A testable design of iterative logic arrays
Author
Parthasarathy, R. ; Reddy, Sudhakar M.
Volume
28
Issue
11
fYear
1981
fDate
11/1/1981 12:00:00 AM
Firstpage
1037
Lastpage
1045
Abstract
Testable design of unilateral iterative logic arrays (ILA) of combinational cells under the assumption of a single cell failure is considered. The concepts of one-step testability and one-step
-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number
of columns and a row so that a faulty cell can be located by a test of length proportional to
, where
is the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell. A set of simpler sufficient conditions are given for the testability of two-dimensional arrays. It is shown that these conditions ensure that all possible input states can be applied to every cell in an array of arbitrary dimensions.
-testability are introduced. Methods to modify the basic cell flow table so as to facilitate fault detection and location are given. It is shown that if no directly observable outputs from each cell are available, then it is possible to augment the cell flow table by the addition of a fixed number
of columns and a row so that a faulty cell can be located by a test of length proportional to
, where
is the number of cells in the array. However, if directly observable outputs are available from each cell, then the test length is shown to be independent of the array length to locate a faulty cell. A set of simpler sufficient conditions are given for the testability of two-dimensional arrays. It is shown that these conditions ensure that all possible input states can be applied to every cell in an array of arbitrary dimensions.Keywords
Cellular logic arrays; Combinational circuit testing; PLA´s, ILA´s, and bit-sliced systems; Circuit faults; Circuit testing; Electrical fault detection; Fabrication; Fault detection; Fault diagnosis; Logic arrays; Logic design; Logic testing; Sufficient conditions;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/TCS.1981.1084934
Filename
1084934
Link To Document