The maximum sampling rate of digital filters under hardware speed constraints

This paper presents a framework for Fiding efficient multiprocessor realizations of digital filters. Based on simple graph-theoretic concepts, a method is derived for determining the minimal sampling period of a given digital filter structure when the speed of arithmetic operations is given but the number of processing units Is unlimited. It Is shown how realistic hardware implementations can be found and evaluated by using the timing diagram of this maximal rate realization as a starting point. The minimal sampling periods of several common digital filter structures are given in terms of addition and multiplication times.