The investigation of board-level vibration for the stacked memory device

The stacked memory device that combined eight single memory units in the vertical direction was investigated in this study when the device was subjected to the random vibrations. The fine computational model of the stacked memory with eight units assembled on board-level was built by ANSYS. The modal analysis was carried out first. By applying the power spectrum according to the GJB-548B standard, the stress and strain distributions of the board-level assembly of the stacked memory device under vibration test conditions were analyzed by the finite element analysis. The critical locations of the boardlevel structure under vibration were identified. The analysis revealed the stress and strain are higher in critical solder joints, which may shorten the life of the joints. The design suggestions for the structure based on the parametric studies were achieved finally.