Stress modeling for the impacts of flip chip process on the ultralow-k chips

ULSI circuits are constantly improved by continuous scaling down the character sizes. Copper connections and the ultralow-k (ULK) materials as inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) were implemented. Therefore, the chip package interaction (CPI) becomes critical due to the mechanical properties deteriorate of ULK with high porosity. The reliability of ULK layer may be affected in flip chip process of the packaging. In this study, a three-dimensional finite element sub-modeling analysis was performed to investigate the stress distribution on Cu/ULK dielectric interconnect structures under flip chip reflow. The ULK layers and Cu connections on the surface of chip were homogenized to an equivalent thin layer, which makes contribution to the global stiffness. Considering the chip surface near the higher stress solder joint, the stresses in the sub-model including Cu/ULK dielectric interconnect structures was examined. The results show that the maximum stress occurs in vias and interfaces between TaN barrier layers and ultralow-k dielectric where the cracks most likely occur.