An experimental 256-Mb DRAM with boosted sense-ground scheme

Author

Asakura, Mikio ; Ooishi, Tsukasa ; Tsukude, Masaki ; Tomishima, Shigeki ; Eimori, Takahisa ; Hidaka, Hideto ; Ohno, Yoshikazu ; Arimoto, Kazutani ; Fujishima, Kazuyasu ; Nishimura, Tadashi ; Yoshihara, Tsutomu

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

29

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

1303

Lastpage

1309

Abstract

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM´s to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm² and a performance of 34 ns access time

Keywords

DRAM chips; integrated memory circuits; 256 Mbit/s; 256-Mb DRAM; 34 ns; boosted sense-ground scheme; cost effective device; data retention characteristics; large process tolerance; largest production volume; semiconductor device; small chip size; Costs; Energy consumption; Fabrication; Leakage current; Power generation; Production; Random access memory; Semiconductor devices; Semiconductor memory; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.328628

Filename

328628