Towards a configurable SoC MPEG-4 advanced simple profile decoder

Author

Garcia, Luis ; Callico, G.M. ; Barreto, D. ; Reyes, V. ; Bautista, T. ; Nunez, A.

Author_Institution

Univ. of Las Palmas de Gran Canaria, Las Palmas

Volume

1

Issue

5

fYear

2007

Firstpage

451

Lastpage

460

Abstract

The evaluation of various architectural designs to allow low bandwidth digital video decoding and reception over the digital audio broadcasting network, and the problem of how to find and implement an optimal HW/SW partition on a Programmable Logic Device with an embedded ARM9 processor are focused. Profiling and design space exploration techniques are applied to the advanced simple profile of an MPEG-4 decoder, for which an innovative SystemC-based system-level design tool, called CASSE, has been used. Simulations results showed that a throughput of 15 QCIF frames per second can be achieved with a low area and low power implementation. Details of this implementation and where the results differ from simulation are presented.

Keywords

decoding; digital audio broadcasting; embedded systems; hardware description languages; logic partitioning; programmable logic devices; system-on-chip; video coding; CASSE SystemC-based system-level design tool; HW/SW partition; MPEG-4 decoder; advanced simple profile SoC MPEG-4 decoder; digital audio broadcasting network; digital video decoding; digital video reception; embedded ARM9 processor; programmable logic device;

fLanguage

English

Journal_Title

Computers & Digital Techniques, IET

Publisher

iet

ISSN

1751-8601

Type

jour

DOI

10.1049/iet-cdt:20060054

Filename

4312770