DocumentCode
1189157
Title
Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns
Author
Thong, Jason ; Nicolici, Nicola
Author_Institution
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada
Volume
17
Issue
9
fYear
2009
Firstpage
1353
Lastpage
1357
Abstract
Common subexpression elimination (CSE) algorithms try to minimize the number of adders (or subtracters) required to implement constant multiplication by searching and substituting common patterns in the CSE representation of a constant. CSE algorithms, in general, cannot find certain patterns due to inherent restrictions in the CSE representation. We propose overlapping digit patterns (ODPs) to remove some of these restrictions. We integrate ODPs into H(k), the best existing heuristic algorithm for single constant multiplication (SCM). H(k) is not applicable to the multiple constant multiplication (MCM) problem, so we cannot consider this problem. Generally, H(k) finds solutions very close to optimal, so there is a strict limitation on any further improvement which applies to any new heuristic. Instead, by integrating ODPs within H(k), we can on average significantly improve the run time of the algorithm (typically by one order of magnitude) while still reducing the number of adders.
Keywords
Hartley transforms; adders; logic circuits; programmable logic devices; adders; common subexpression elimination algorithms; overlapping digit patterns; subtracters; time-efficient single constant multiplication; Common subexpression elimination (CSE); overlapping digit patterns (ODPs); run time efficiency; single constant multiplication (SCM);
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2008.2003004
Filename
4799221
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