DocumentCode
1190038
Title
The JAFARDD processor: a Java architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing
Author
El-Kharashi, M. Watheq ; Gebali, Fayez ; Li, Kin F. ; Zhang, Fang
Author_Institution
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Volume
48
Issue
4
fYear
2002
fDate
11/1/2002 12:00:00 AM
Firstpage
1004
Lastpage
1015
Abstract
This paper presents the JAFARDD (a Java Architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing) processor. JAFARDD dynamically translates Java stack-dependent bytecodes to RISC-style stack-independent instructions to facilitate the use of a general-purpose RISC core. JAFARDD enables the exploitation of instruction level parallelism among the translated instructions by the use of bytecode folding coupled with Tomasulo´s algorithm. We detail the JAFARDD architecture and the global architecture design principles observed while designing each pipeline module. We also illustrate the flow of the Java bytecodes through each of the processing phases. Benchmarking of JAFARDD using SPECjvm98 has shown a performance improvement between 1.10 and 2.25.
Keywords
Java; digital signal processing chips; parallel architectures; pipeline processing; reduced instruction set computing; JAFARDD architecture; JAFARDD processor; Java architecture; Java stack-dependent bytecodes; RISC-style stack-independent instructions; SPECjvm98; Tomasulo´s algorithm; dual processing; dynamic translation; folding algorithm; general-purpose RISC core; global architecture design; instruction level parallelism; pipeline module; reservation stations; Computer architecture; Dynamic scheduling; Hardware; Java; Mobile handsets; Parallel processing; Pipeline processing; Reduced instruction set computing; Switches; Virtual machining;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/TCE.2003.1196432
Filename
1196432
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