Improving the accuracy and efficiency of junction capacitance characterization: strategies for probing configuration and data set size

Author

MacSweeney, Dermot ; McCarthy, Kevin G. ; Floyd, Liam ; Duane, Russell ; Hurley, Paul ; Power, James A. ; Kelly, Sean C. ; Mathewson, Alan

Author_Institution

Cypress Semicond., Cork, Ireland

Volume

16

Issue

2

fYear

2003

fDate

5/1/2003 12:00:00 AM

Firstpage

207

Lastpage

214

Abstract

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.

Keywords

bipolar integrated circuits; bipolar transistors; capacitance measurement; current-mode logic; integrated circuit measurement; integrated circuit modelling; measurement errors; parameter estimation; bipolar current mode logic; bipolar depletion capacitances; bootstrapping technique; configuration probing; data set size; four-probe method; junction depletion capacitance; model accuracy; on-wafer measurement; parameter extraction; probing configurations; submicron BiCMOS process; Capacitance measurement; Cutoff frequency; Integrated circuit modeling; Logic devices; Logic gates; Parasitic capacitance; Power measurement; Scattering parameters; Substrates; Testing;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2003.811577

Filename

1198030