Advanced process device technology for 0.3-μm high-performance bipolar LSIs

Author

Tamaki, Yoichi ; Shiba, Takeo ; Kure, Tokuo ; Ohyu, Kiyonori ; Nakamura, Tohru

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

39

Issue

6

fYear

1992

fDate

6/1/1992 12:00:00 AM

Firstpage

1387

Lastpage

1391

Abstract

A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm², and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (f_T) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between f_T and base resistance is also discussed

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; integrated logic circuits; large scale integration; 0.3 micron; 27 ps; 50 GHz; ECL; U-SICOS; U-groove isolated sidewall base contact structure; base resistance; bipolar LSIs; cutoff frequency; emitter width; fabrication; gate delay time; graft bases; isolation width; process device technology; shallow emitters formation; tradeoff; Bipolar integrated circuits; Boron; Cutoff frequency; Delay effects; Electrodes; Ion implantation; Isolation technology; Large scale integration; Parasitic capacitance; Transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.137318

Filename

137318