A new design methodology for multiport SRAM cell

Author

Lai, Feipei ; Chuang, Ying Lang ; Chen, Shyh Jong

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

41

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

677

Lastpage

685

Abstract

In this paper, we propose a new design methodology for multiport SRAM cell. A traditional static 6T CMOS cell is adapted to the multiport SRAM cell by adding several wordline transistors, thereby allowing asynchronous reads and writes during an operands access stage using the read feature of the 5T cell and the write feature of the 6T cell. The stability of the SRAM cell is affected by the factors of p-transistor, n-transistor and pass-transistor, not by the absolute dimensions of the three transistors. The optimal read access curve can be used to obtain the fastest access time in the secure range for the general multiport SRAM cell

Keywords

CMOS memory circuits; SRAM chips; circuit stability; integrated circuit design; asynchronous reads; asynchronous writes; design methodology; multiport SRAM cell; operands access stage; optimal read access curve; stability; static 6T CMOS cell; static RAM; wordline transistors; Circuit simulation; Clocks; Computer science; Costs; Design methodology; Electric variables; Microarchitecture; Random access memory; Read-write memory; Robust stability;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.331519

Filename

331519