A 100-Msps sampling analog-to-digital converter chip set

Author

Imamura, Makoto ; Kusayanagi, Naoya ; Toyama, Akira ; Choi, Toru

Author_Institution

Yokogawa Electr. Corp., Tokyo, Japan

Volume

41

Issue

2

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

208

Lastpage

211

Abstract

The authors describe a 100-Msps sampling analog-to-digital converter (ADC) chip set that can be used for a wideband high-resolution digital storage oscilloscope (DSO). A high conversion rate and a 500-MHz sampling bandwidth with an 8-b effective resolution are obtained by a combination of three Si-bipolar chips and two GaAs-diode chips. the ADC uses a pipelined two-step subranging architecture that uses two cascade wideband track-and-hold (T/H) circuits. The design features of the T/H circuits and the residual amplifier are also presented

Keywords

III-V semiconductors; analogue-digital conversion; cathode-ray oscilloscopes; digital instrumentation; elemental semiconductors; gallium arsenide; silicon; 500 MHz; A/D convertor; GaAs diode chips; Si bipolar chips; cascade wideband track-and-hold circuits; pipelined two-step subranging architecture; residual amplifier; sampling analog-to-digital converter chip; wideband high-resolution digital storage oscilloscope; Analog-digital conversion; Bandwidth; Bridge circuits; Clocks; Gallium arsenide; Oscilloscopes; Sampling methods; Schottky diodes; Switches; Wideband;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/19.137349

Filename

137349