• DocumentCode
    1195764
  • Title

    Parallel design of arithmetic coding

  • Author

    Jiang, J. ; Jones, S.

  • Author_Institution
    Sch. of Eng., Bolton Inst. of Higher Educ., UK
  • Volume
    141
  • Issue
    6
  • fYear
    1994
  • fDate
    11/1/1994 12:00:00 AM
  • Firstpage
    327
  • Lastpage
    333
  • Abstract
    The paper presents a parallel algorithm design for real-time implementation of arithmetic coding. The implementation comprises a parallel-processing array arranged in a tree structure. Within each cycle, a group of input symbols can be encoded. This increases the arithmetic coding speed substantially. Details of a fixed-precision algorithm design, its implementation and simulation of its performance are reported
  • Keywords
    digital arithmetic; encoding; parallel algorithms; arithmetic coding; fixed-precision algorithm design; parallel algorithm design; parallel design; parallel-processing array; real-time implementation; tree structure;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:19941387
  • Filename
    331616
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1195764