• DocumentCode
    1196423
  • Title

    Equivalent Dominant Pole Approximation of Capacitively loaded VLSI Interconnection

  • Author

    Zurada, Jozef

  • Volume
    34
  • Issue
    2
  • fYear
    1987
  • fDate
    2/1/1987 12:00:00 AM
  • Firstpage
    205
  • Lastpage
    207
  • Abstract
    The equivalent dominant pole approximation including delay term is proposed for the transient response calculation of an uniformly distributed URC line loaded with capacitance. Transfer functions for voltage and current excitations have been derived and their applications for modeling of VLSI interconnections have been discussed.
  • Keywords
    Distributed-parameter circuits, RC; Integrated circuit interconnections; Interconnections, Integrated circuits; Poles and zeros, linear systems; VLSI; Very large-scale integration (VLSI); Circuits; Data communication; Graph theory; Interpolation; Mathematics; Sampling methods; Signal analysis; Tree graphs; Very large scale integration; Wave functions;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/TCS.1987.1086108
  • Filename
    1086108
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1196423