A test methodology for wafer scale system

To efficiently access and control on-chip design for test (DFT) circuitry, a standard test interface is required. A uniform testing interface is defined for each functional cell, with built-in self-test incorporated whenever possible. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of different functional cell types. Details are provided for the function, cell, and wafer level testing standards as well as for the procedures to be followed at wafer level restructuring and test. The test overhead area required is assessed; and for a large class of designs, the benefit of reduced input/output (I/O) area is found to more than compensate for the added test area