Modelling multiple faults in fault-tolerant processor architectures

The fault-tolerant microprocessor systems used in safety-critical applications need to be thoroughly validated during the design stages. As feature sizes reduce in future CMOS technologies, there is an increased probability of transient and intermittent faults. A new model for multiple bit-flips in the time domain is proposed, which can be used to target fault injection experiments. This extends the single or multiple bit-flip model that is currently used. Some results from fault injection experiments on two different processor architectures are also presented to illustrate the applicability of this model.