Error analysis in pipeline A/D converters and its applications

The conversion error of a pipelined A/D converter using inaccurate comparators is analyzed. Error bounds are established, and it is shown that the error can be compensated using simple analog circuitry combined with some digital logic. The resulting system is especially useful for fast converters in which accurate compensators would require a large chip area and large DC power. Simulations are presented to verify the efficiency of the proposed error correction scheme