• DocumentCode
    1199514
  • Title

    A 0.18-μm CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML

  • Author

    Choi, Goang Seog ; Kim, Joo Seon ; Park, Hyun Jeong ; Ahn, Young Jun ; Park, Hyun Soo ; Bae, Jum Han ; Park, In Sik ; Shin, Dong Ho

  • Author_Institution
    Samsung Electron. Co. Ltd., Kyunggi, South Korea
  • Volume
    40
  • Issue
    1
  • fYear
    2005
  • Firstpage
    342
  • Lastpage
    350
  • Abstract
    This paper describes a front-end processor for Blu-Ray Disc (BD) recorder applications. It integrates a partial response maximum likelihood (PRML) block, a data processor (DP) block, and a servo block. The PRML includes an analog-to-digital converter (ADC) and two digitally controlled oscillators (DCO) for data phase-locked loop (PLL) and wobble PLL. A nonlinear equalizer is designed to compensate for high-frequency signal components without increasing inter-symbol interference (ISI). A Teaklite DSP, an ADC, and a digital-to-analog converter are embedded for servo controls. The functions of 17PP modem and error correction code (ECC) are also implemented. Due to the proposed nonlinear equalizer in PRML, less than 2 × 10-4 of symbol-error rate (SER), defined in the Blu-Ray Disc format book, is achieved with tangential tilt margin of ±0.5°. This system on a chip (SOC) is fabricated in 0.18-μm one-poly five-metal CMOS technology. It contains 12 million transistors in a 50-mm2 die and consumes 0.9 W with a channel clock of 132 MHz in 2× playback mode.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; digital phase locked loops; error correction codes; maximum likelihood decoding; optical disc storage; oscillators; recorders; system-on-chip; 0.18 micron; 0.9 W; 132 MHz; Blu-Ray Disc recorder; CMOS front-end processor; Teaklite DSP; adaptive PRML; analog-to-digital converter; data phase-locked loop; data processor; digitally controlled oscillators; error correction code; high-definition television; high-frequency signal components; inter-symbol interference; nonlinear equalizer; partial response maximum likelihood block; servo block; symbol-error rate; system on a chip; tilt margin; wobble PLL; Analog-digital conversion; CMOS process; CMOS technology; Digital control; Equalizers; Error correction codes; Oscillators; Phase locked loops; Servomechanisms; Signal design; 23 GB; Blu-Ray Disc (BD); CMOS; FPBDR; data processor (DP); error correction code (ECC); high-definition television (HDTV); nonlinear; partial response maximum likelihood (PRML); phase-locked loop (PLL); radio frequency (RF); recorder; symbol error rate (SER); system-on-chip (SOC); tilt margin;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2004.837933
  • Filename
    1375018