• DocumentCode
    1199862
  • Title

    Advanced OSELO isolation with shallow grooves for high-speed submicrometer ULSIs

  • Author

    Kaga, Toru ; Kawamoto, Yoshifumi ; Ijima, S. ; Sudoh, Yoshimi ; Sakai, Yoshio

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • Volume
    35
  • Issue
    7
  • fYear
    1988
  • fDate
    7/1/1988 12:00:00 AM
  • Firstpage
    893
  • Lastpage
    898
  • Abstract
    A submicrometer (0.7-μm) isolation structure using processes that are compatible with the LOCOS processes has been developed. This novel isolation structure, called OSELO II, is fabricated using modified local oxidation technology and an offset structure. The offset structure is characterized by a framed Si3N4 mask for bird-beak-free oxidation, formation of shallow self-aligned Si grooves, and two-step boron-ion implantation that decreases current leakage along the isolation sidewall. This isolation technology provides (1) an active MOS transistor having a mask-defined 0.8-μm channel width giving 60% more drain current than the conventional transistor with LOCOS isolation (2) 0.6-μm minimum isolation length, which equals the isolation length between the two adjacent active transistors and is also defined by the mask length, and (3) 20% lower parasitic junction capacitance compared with the LOCOS structure. These results demonstrate that the process is promising for high-speed submicrometer ultralarge-scale integrated devices
  • Keywords
    VLSI; integrated circuit technology; ion implantation; 600 to 800 nm; B ion implantation; LOCOS compatible; OSELO II; OSELO isolation; Si grooves; ULSI; bird-beak-free oxidation; decreases current leakage; framed Si3N4 mask; isolation length; isolation structure; isolation technology; lower parasitic junction capacitance; modified local oxidation technology; more drain current; offset structure; self-aligned Si grooves; shallow grooves; submicrometer ultralarge-scale integrated devices; Doping; Etching; Fabrication; Impurities; Isolation technology; MOSFETs; Oxidation; Parasitic capacitance; Silicon; Ultra large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.3341
  • Filename
    3341