Statistical methods for the estimation of process variation effects on circuit operation

In this paper, a technology computer-aided design (TCAD) driven method for accurate prediction of the performance spread of integrated circuits due to process variations is presented. The methodology starts with the development of the nominal process recipe and process simulators are calibrated to an existing process to obtain nominal device characteristics. After determining nominal process parameters, their variations are introduced followed by screening experiments to determine the relative effects of given process variations on the input-output delay and the average power dissipation in a circuit. Response surface models (RSMs) are then generated based on critical process factors identified. Process parameter optimization is performed using these RSM models to tune the mean circuit performance and to improve the yield. This methodology is demonstrated on a 33-stage ring oscillator manufactured with a CMOS design flow. The proposed methodology maps the process domain to design space, and plays a key role in design for manufacturability (DFM) to quantify direct impact of the process variations on circuits.