DocumentCode
1204863
Title
Voltage-mode CMOS quaternary latch circuit
Author
Current, K.W.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA
Volume
30
Issue
23
fYear
1994
fDate
11/10/1994 12:00:00 AM
Firstpage
1928
Lastpage
1929
Abstract
A new voltage-mode CMOS quaternary threshold logic latch circuit that has been realised in a standard 2 μm p-well polysilicon-gate CMOS technology is presented. This circuit requantises quaternary logical voltages during a SETUP clock mode and latches the input value during the HOLD clock mode. Using a 5 V supply and logical voltage increments of 1.67 V, the quaternary latch has a worst-case total SETUP and HOLD time of ~5.7 ns. and best single-level transition total SETUP and HOLD time of ~0.9 ns
Keywords
CMOS logic circuits; flip-flops; multivalued logic; threshold logic; 0.9 ns; 2 micron; 5 V; 5.7 ns; CMOS quaternary latch circuit; HOLD clock mode; SETUP clock mode; p-well polysilicon-gate CMOS technology; threshold logic; voltage-mode;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19941299
Filename
335669
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