FPGA based partial reconfigurable fir filter design

This paper proposes partial reconfigurable FIR filter design using systolic Distributed Arithmetic (DA) architecture optimized for FPGAs. To implement computationally efficient, low power, high speed Finite Impulse Response (FIR) filter a two dimensional fully pipelined structure is used. To reduce the partial reconfiguration time a new architecture for the Look-Up Table (LUT) in distributed arithmetic is proposed. The FIR filter is dynamically reconfigured to realize low pass and high pass filter characteristics by changing the filter coefficients in the partial reconfiguration module. The design is implemented using XUP Virtex 5 LX110T FPGA kit. The FIR filter design shows improvement in configuration time and efficiency.