A hardware accelerator based system for ATPG of sequential circuits

The design complexity of VLSI electronic circuits has posed major problems for test engineers, and the combined tasks of fault simulation and test pattern generation are becoming the major bottleneck in the design and verification process. This article presents a system which merges a test generation technique capable of handling highly sequential circuits in combination with a concurrent fault simulation algorithm implemented in hardware, resulting in a high-performance automatic test pattern generator. Evidence is presented which demonstrates the successful integration of this system.