DocumentCode
1214447
Title
Regular pipelined multipliers
Author
Luk, Wayne
Author_Institution
Comput. Lab., Oxford Univ., UK
Volume
25
Issue
20
fYear
1989
Firstpage
1405
Lastpage
1407
Abstract
Two regular processor arrays for multiplying unsigned numbers are described. The essence is a structure that allows designs with different degrees of pipelining to be synthesised. The impact of varying the degree of pipelining on performance is assessed.
Keywords
digital arithmetic; multiplying circuits; multiprocessing systems; pipeline processing; carry-save algorithm; performance aspects; pipelined multipliers; regular processor arrays; shift-add algorithm; unsigned numbers multiplication;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19890940
Filename
34026
Link To Document