Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

Author

Tuuna, Sampo ; Zheng, Li-Rong ; Isoaho, Jouni ; Tenhunen, Hannu

Author_Institution

Dept. of Inf. Technol., Univ. of Turku, Turku

Volume

16

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

766

Lastpage

770

Abstract

In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance-inductance-capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.

Keywords

RLC circuits; integrated circuit noise; power supply circuits; switched current circuits; transmission lines; HSPICE; RLC segments; distributed resistance-inductance-capacitance lines; driver skewing times; on-chip bus switching current; on-chip power supply grid model; power supply noise; switching patterns; Distributed parameter circuits; Integrated circuit interconnections; Integrated circuit noise; Network-on-a-chip; Power supplies; Power system modeling; Power transmission lines; Semiconductor device modeling; Voltage; Wires; Bus; power supply noise; transmission line;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2000258

Filename

4515958