A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC

Author

Toyokura, Masaki ; Kodama, Hisahi ; Miyagoshi, Eiji ; Okamoto, Koyoshi ; Gion, Masahiro ; Minemaru, Takayuki ; Ohtani, Akihiko ; Araki, Toshiyuki ; Takeno, Hiroshi ; Akiyama, Toshihide ; Wilson, Brent ; Aono, Kunitoshi

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

29

Issue

12

fYear

1994

fDate

12/1/1994 12:00:00 AM

Firstpage

1474

Lastpage

1481

Abstract

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2´s and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V

Keywords

CMOS integrated circuits; codecs; digital signal processing chips; motion estimation; pipeline processing; vector processor systems; video codecs; video signal processing; 0.5 micron; 100 MHz; 15.00 mm; 17.00 mm; 3.3 V; 4.2 W; 80 MHz; MPEG2 CODEC; SIMD type vector-pipeline architecture; VDSP2; macroblock-level-pipeline architecture; motion estimation unit; power dissipation; real-time decoder; real-time encoder; triple-layer-metal CMOS technology; video DSP; CMOS technology; Decoding; Digital signal processing; Discrete cosine transforms; Image storage; Motion estimation; Pipelines; Quantization; Standards development; Video codecs;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.340420

Filename

340420