The effect of layout modification on latchup triggering in CMOS by experimental and simulation approaches

Author

De la Rochette, Hélène ; Bruguier, Guy ; Palau, Jean Marie ; Gasiot, Jean ; Ecoffet, Robert

Author_Institution

Centre d´´Electron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Volume

41

Issue

6

fYear

1994

Firstpage

2222

Lastpage

2228

Abstract

The influence of certain geometrical parameters on latchup triggering in CMOS-1.2 /spl mu/m structure is studied by means of experiments and simulations on test structures. Electrical characterizations are made in order to validate quantitatively the analysis achieved by numerical simulations. The results of heavy ion irradiation from two different sources are given and discussed with regard to the influence of the same geometrical parameters on the sensitivity of the test structures to latchup.<>

Keywords

CMOS integrated circuits; electrical faults; integrated circuit layout; integrated circuit reliability; ion beam effects; numerical analysis; simulation; 1.2 micron; CMOS IC; electrical characterizations; geometrical parameters; heavy ion irradiation; latchup sensitivity; latchup triggering; layout modification; monolithic IC layout; numerical simulation; CMOS technology; Circuit testing; Doping; Gain measurement; Implants; Manufacturing; Numerical simulation; Predictive models; Solid modeling; Steady-state;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.340566

Filename

340566