A new CMOS NAND logic circuit for reducing hot-carrier problems

Author

Park, Heung-Joon ; Lee, Kwyro ; Kim, Choong-ki

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

Volume

24

Issue

4

fYear

1989

fDate

8/1/1989 12:00:00 AM

Firstpage

1041

Lastpage

1047

Abstract

The circuit, which uses a design concept called the self-bootstrapping method (SBM), lowers the channel electric field in the n-MOSFET during switching transients, leading to the suppression of the n-MOSFET substrate current. Experimental and simulation results show that about 3.9 times smaller peak substrate current is obtained in the NAND logic circuits with SBM when compared to the conventional NAND logic circuit. The circuit also gives shorter rise and fall times and better noise margin. The SBM concept provides highly reliable CMOS NAND logic without any change in device structure and/or fabrication process

Keywords

CMOS integrated circuits; NAND circuits; hot carriers; integrated logic circuits; CMOS NAND logic circuit; channel electric field; device structure; fall times; hot-carrier problems; n-MOSFET; noise margin; self-bootstrapping method; substrate current; switching transients; CMOS logic circuits; CMOS process; Circuit noise; Circuit simulation; Fabrication; Hot carriers; Logic circuits; Logic devices; MOSFET circuits; Switching circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.34090

Filename

34090