DocumentCode
1220347
Title
Multipartite table methods
Author
De Dinechin, Florent ; Tisserand, Arnaud
Author_Institution
Arenaire Project, Ecole Normale Superieure de Lyon, France
Volume
54
Issue
3
fYear
2005
fDate
3/1/2005 12:00:00 AM
Firstpage
319
Lastpage
330
Abstract
A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at http://www.ens-lyon.fr/LIP/Arenaire/.
Keywords
computer architecture; digital arithmetic; field programmable gate arrays; table lookup; Virtex FPGA; bipartite table; computer arithmetic; elementary function evaluation; hardware operator; multipartite table; table-lookup-and-addition method; Arithmetic; Computer architecture; Cost function; Field programmable gate arrays; Hardware; Iterative algorithms; Polynomials; Signal processing; Space exploration; Table lookup;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2005.54
Filename
1388196
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