Design and optimization of vertical SiGe thyristors for on-chip ESD protection

Author

Joshi, Sopan ; Ida, Richard ; Rosenbaum, Elyse

Author_Institution

Univ. of Illinois, Urbana, IL, USA

Volume

4

Issue

4

fYear

2004

Firstpage

586

Lastpage

593

Abstract

We present extensive measurement results investigating the design and optimization of vertical SiGe thyristors for use as ESD protection elements in RF integrated circuits. Experiments include variations of the anode material, contact geometry, and buried layer, as well as a detailed study of optimal area scaling. RF characterization using S-parameter data is presented.

Keywords

BiCMOS analogue integrated circuits; Ge-Si alloys; S-parameters; electrostatic discharge; heterojunction bipolar transistors; integrated circuit design; integrated circuit reliability; radiofrequency integrated circuits; thyristors; RF characterization; RF integrated circuits; S-parameter data; SiGe; anode material; buried layer; contact geometry; electrostatic discharges; heterojunction bipolar transistors; on-chip ESD protection; optimal area scaling; reliability; vertical SiGe thyristors; Anodes; Design optimization; Electrostatic discharge; Germanium silicon alloys; Integrated circuit measurements; Protection; Radio frequency; Radiofrequency integrated circuits; Silicon germanium; Thyristors;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2004.838423

Filename

1388429