Extension and source/drain design for high-performance FinFET devices

Author

Kedzierski, Jakub ; Ieong, Meikei ; Nowak, Edward ; Kanarsky, Thomas S. ; Zhang, Ying ; Roy, Ronnen ; Boyd, Diane ; Fried, David ; Wong, H. S Philip

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

50

Issue

4

fYear

2003

fDate

4/1/2003 12:00:00 AM

Firstpage

952

Lastpage

958

Abstract

Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the <100> and <100> directions showing different transport properties.

Keywords

doping profiles; field effect transistors; ion implantation; semiconductor device measurement; 30 nm; angled extension implants; device resistance; double gate devices; fin thickness; gate lengths; high-performance FinFET devices; on-currents; parasitic series resistance; selective silicon epitaxy; short channel effects; source/drain design; transport properties; Contact resistance; Epitaxial growth; FinFETs; Immune system; Implants; Microelectronics; Scalability; Silicides; Silicon; Transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2003.811412

Filename

1206877