• DocumentCode
    1226288
  • Title

    Silicon germanium programmable circuits for gigahertz applications

  • Author

    Guo, J.-R. ; You, C. ; Chu, M. ; Curran, P.F. ; Diao, J. ; Goda, B. ; Jin, P. ; Kraft, R.P. ; McDonald, J.F.

  • Author_Institution
    IBM, NY
  • Volume
    1
  • Issue
    1
  • fYear
    2007
  • fDate
    2/1/2007 12:00:00 AM
  • Firstpage
    27
  • Lastpage
    33
  • Abstract
    Implementation of a silicon germanium (SiGe) field programmable gate array (FPGA) has been described. The reconfigurable basic cell (BC) that evolved from the Xilinx XC6200 has been redesigned to achieve high speed with lower power consumption. The propagation delay of the BC in comparison to the BC implemented in the earlier generation SiGe process has been reduced to 18% of its original value (from 240 to 42 ps) and the power consumption has been comparably reduced. The range of power reduction is from 13% of its original value when the BC is fully turned on down to 2% when the power saving scheme is applied. A 20times20 SiGe FPGA with physical dimensions of 4.5times4.8 mm has been fabricated using the IBM 120 GHz (7HP) process. To deliver a 10 GHz clock, an H tree has been designed and implemented with reduced skew. To demonstrate its performance, a 4:1 multiplexer (MUX) has been mapped for comparison with various CMOS FPGAs. The SiGe FPGA can achieve an 8 Gbps transmission rate, which is a 40 times improvement over the same implementation on a Xilinx Virtex CMOS FPGA. Other comparisons between the SiGe FPGA and commercial FPGAs have also been included. From simulations and measurements, the SiGe FPGAs have been shown to have high performance that can successfully tackle gigahertz applications
  • Keywords
    CMOS integrated circuits; Ge-Si alloys; MMIC; clocks; current-mode logic; field programmable gate arrays; low-power electronics; trees (electrical); 10 GHz; 120 GHz; 4.5 mm; 4.8 mm; 8 Gbit/s; CMOS FPGA; H tree; SiGe; Xilinx XC6200; clock; field programmable gate arrays; gigahertz applications; multiplexer; power consumption; power saving scheme; propagation delay; reconfigurable basic cell; silicon germanium; skew;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices & Systems, IET
  • Publisher
    iet
  • ISSN
    1751-858X
  • Type

    jour

  • DOI
    10.1049/iet-cds:20050065
  • Filename
    4123972