DocumentCode
122729
Title
MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization
Author
Karunagaran, Sriram ; Sahoo, Karuna P. ; Poroor, Jayaraj ; Fujita, Masayuki
Author_Institution
Amrita Vishwa Vidyapeetham, Kollam, India
fYear
2014
fDate
15-17 April 2014
Firstpage
237
Lastpage
248
Abstract
In the product development life-cycle of hard-real-time embedded systems, software verification plays a very important role. During verification, a Hardware-In-Loop (HIL) testbed is used to test the key properties of the software, namely, schedulability, concurrency and timeliness, by exercising and monitoring the interfaces of the Design Under Test (DUT). Often, building a testbed to test these properties can be challenging and costly. For the first time, this paper proposes a Modular Architecture with Event-driven Synchronization and Time-driven Real-time Operations (MAESTRO) for a low-cost testbed, to support HIL and system testing. Our proposed MAESTRO-based testbed is compared with other testbeds and is shown to provide superior performance. Finally, the paper also defines key properties essential for building a robust embedded testbed.
Keywords
embedded systems; program testing; program verification; scheduling; synchronisation; DUT; HIL; MAESTRO; design under test; hard-real-time embedded systems; hardware-in-loop testbed; modular architecture with event-driven synchronization and time-driven real-time operations; product development life-cycle; robust embedded testbed; schedulability; software verification; time-driven embedded testbed architecture; Computer architecture; Hardware; Monitoring; Real-time systems; Software; Testing; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th
Conference_Location
Berlin
ISSN
1080-1812
Print_ISBN
978-1-4799-4691-4
Type
conf
DOI
10.1109/RTAS.2014.6926006
Filename
6926006
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