Analysis of stability issues and power efficiency of symmetric and asymmetric low power nanoscaled SRAM cells

Over the period of advancements in technology, stability and power-efficiency of the memory cells have proven to be the dire urges. And this has led to the development of various static memory cell topologies. In this paper, analysis of very important factors of merits of Static Random Access Memory (SRAM) i.e. Static Noise Margin (SNM) and total power consumption in 6T, 8T and 5T SRAM cells designed at 65nm UMC CMOS technology is done. The work includes a vivid description of the factors like applied voltage (Vdd) and different process corners affecting the SNMs and power consumption variations along with the simulations. The simulations are well in agreement with the expectations based on the different cell structures and their functionalities.