DocumentCode
1229462
Title
Delay Uncertainty Reduction by Gate Splitting
Author
Agarwal, Vineet ; Sun, Jin ; Wang, Janet M.
Author_Institution
Intel Corp., Folsom, CA
Volume
56
Issue
4
fYear
2009
fDate
4/1/2009 12:00:00 AM
Firstpage
295
Lastpage
299
Abstract
Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates.
Keywords
delays; field effect transistors; delay uncertainty reduction; effective splitting-based variation reduction; gate delay; gate splitting; primary output; timing-variation reduction; Delay uncertainty reduction; gate cloning; gate split; process variation;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2009.2015394
Filename
4812091
Link To Document