Efficient region-aware P/G TSV planning for 3D ICs

Power delivery network (PDN) design is one of the most critical challenges in 3D Integrated Circuits (IC) design. In existing studies, to ensure the robustness of the 3D PDN, the number of TSVs was always increased inefficiently to mitigate the IR-drop and power noise. However, the overhead for connections is a crucial obstacle to the development of 3D ICs. Consequently, an efficient TSV topology is needed to reduce the overhead of TSVs while meeting the power supply requirements. The redundant TSVs may introduce more keep-out zones, decrease the core utilization of the chip, and lead to high cost. In this paper, we propose a region-aware TSV planning algorithm which can distribute TSV resources non-evenly over different areas according to their IR-drop constraints separately. This method can use fewer power TSVs to meet the power integrity constraint of the whole chip while guaranteeing the functionality. Furthermore, to ensure the practicability, we also take the whitespace into account. Experimental results show that, the proposed algorithm can save on average 42% and 27% power TSV resources without and with whitespace consideration respectively compared with the evenly TSV planning algorithm.