Delay and power optimization with TSV-aware 3D floorplanning

3D technology facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals, and the RC value of a single TSV depends on TSV dimensions, technology and used materials. The impact of TSVs on the delay also depends on the interaction between neighboring TSVs, on the length of wires connected to TSVs, and physical parameters of metal layers the wires are assigned to. Wire length reduction and number of TSVs influences the number of needed buffers. The dynamic power consumption of 3D-interconnects includes power consumption in wires, TSVs and buffers. Therefore, it is crucial to consider RC values of TSVs early in the design phase to evaluate and optimize electrical performance of 3D ICs. We use TSV-aware 3-D floorplanning tool that concurrently places TSV islands with circuit blocks. During the optimization we take into account TSV contribution to area, delay and power. TSVs are arranged in the islands with given dimension and pitch. Including TSV contribution into cost function during optimization reduces peak and total delay in interconnects by 32% and 20% respectively as compare to TSV delay-unaware floorplanning. It also allows for more accurate estimation of the number of buffers and reduction in interconnect dynamic power consumption by 7%-11%.