An efficient pipelined FFT architecture

Author

Chang, Yun-Nan ; Parhi, Keshab K.

Author_Institution

Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

Volume

50

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

322

Lastpage

325

Abstract

This paper presents an efficient VLSI architecture of the pipeline fast Fourier transform (FFT) processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By combining both the feedforward and feedback commutator schemes, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

Keywords

circuit feedback; digital integrated circuits; digital signal processing chips; fast Fourier transforms; feedforward; pipeline arithmetic; digit-serial arithmetic units; discrete-time signal processing algorithms; efficient VLSI architecture; feedback commutator schemes; feedforward commutator schemes; hardware utilization; overall ROM size reduction; pipelined FFT architecture; radix-4 decimation-in-time algorithm; twiddle factor storage; Algorithm design and analysis; Arithmetic; Computer architecture; Discrete Fourier transforms; Fast Fourier transforms; Hardware; Pipelines; Read only memory; Signal processing algorithms; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2003.811439

Filename

1209310