DocumentCode
1231686
Title
Integrated scheduling, allocation and module selection for design-space exploration in high-level synthesis
Author
Ahmad, I. ; Dhodhi, M.K. ; Chen, C.-Y.R.
Author_Institution
Dept. of Electr. & Comput. Eng., Kuwait Univ., Safat, Kuwait
Volume
142
Issue
1
fYear
1995
fDate
1/1/1995 12:00:00 AM
Firstpage
65
Lastpage
71
Abstract
High-level synthesis consists of many interdependent tasks such as scheduling, allocation and binding. To make efficient use of time and area, functional unit allocation must be performed using a library of modules which contains a variety of module types with identical functionality, but different area and delay characteristics. The synthesis technique presented in the paper simultaneously performs scheduling, allocation and module selection, using problem-space genetic algorithm (PSGA) to produce area and performance optimised designs. The PSGA-based system uses an intelligent design-space exploration technique by combining a genetic algorithm with a simple and fast problem-specific heuristic to search a large design space effectively and efficiently. The efficient exploration of design-space is essential to design cost-effective architectures for problems of VLSI/ULSI complexity. The PSGA method offers several advantages such as the versatility, simplicity, objective independence and the computational advantages for problems of large size over other existing techniques. The proposed synthesis system handles multicycle functional units, chaining, conditional constructs, loops and structural pipelining. Experiments on benchmarks show very promising results
Keywords
circuit CAD; computational complexity; genetic algorithms; high level synthesis; scheduling; VLSI/ULSI complexity; area; benchmarks; chaining; delay; design-space exploration; functional unit allocation; genetic algorithm; high-level synthesis; identical functionality; integrated allocation; integrated scheduling; loops; module selection; multicycle functional unit; problem-space genetic algorithm; structural pipelining; versatility;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19951516
Filename
350880
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